1. Field of the Invention
It is related to a variable delay circuit.
2. Description of Related Art
Japanese Laid-open Patent Publication No. 10-242817 discloses a delay circuit that controls the delay time of a rising edge and a falling edge by using two transfer gates. FIG. 1 shows the circuit diagram of the pulse width variable circuit disclosed in Japanese Laid-open Patent Publication No. 10-242817.
When the level of an input pulse signal IN changes from “L” to “H,” NMOS126 is turned on and a current path I2 becomes conductive. When the level of input pulse signal IN changes from “H” to “L,” NMOS122 is turned on and a current path I1 becomes conductive. The input pulse signal IN is propagated to a buffer 131 via the current path I1 or the current path I2. The signal propagation delay time in each current path I1 and I2 is set respectively depending on the resistance values of transfer gates 121 and 125 that change respectively according to control signals S11 and S12 and the capacity of a capacitor 124.
In addition, the technology that relates to a delay circuit is disclosed in Japanese Laid-open Patent Publication No. 4-172811 and Japanese Laid-open Patent Publication No. 6-61810.